1. Field of the Invention
The present invention relates to a fast frequency hopping spread spectrum receiver used in digital mobile radio communication or the like, and a correlator and synchronizer that are assembled therein, and more particularly to those in which synchronization of a hopping sequence is made acquirable at a high speed.
2. Description of the Related Art
In a frequency hopping spread spectrum system used in a digital mobile radio communication system or the like, transmission is carried out by cutting and dividing narrow-band modulated signals in phase shift keying (PSK), frequency shift keying (FSK) or the like in pieces time-wise so as to disperse them in a plurality of frequency bands (frequency slots) as shown in FIG. 1. A piece of the signal cut and divided in pieces is called a "chip" and the length thereof is referred to as a chip period Tc (sec). A system of setting the chip period Tc to a bit period Tb or below is called Fast Frequency Hopping Spread Spectrum (abbreviated hereinafter as FFHSS) system. Besides, that in which the chip period Tc exceeds the bit period Tb is called slow frequency hopping.
When it is assumed in fast frequency hopping that a hopping sequence length is M, there is the relationship Tb=M.multidot.Tc. The arrangement of chip signals follows the hopping sequence given individually to respective users. When FIG. 1 is taken as an example, it is shown that the hopping sequence length M is 4, and the adopted hopping sequence is "1, 4, 2, 3". Four chip signals that constitute one bit are arranged in the frequency bands of f.sub.1, f.sub.4, f.sub.2 and f.sub.3, respectively. It is possible to standardize the communication quality by having a carrier frequency change finely as described above so that the signals are constituted so as not to stay long at a frequency in a bad communication state.
As shown in FIG. 2, a conventional FFHSS receiver is provided with a receiving antenna 1 for receiving an electric wave (an FFHSS signal), a local oscillator 3 for generating a signal for shifting a frequency band of a received signal to a band of an intermediate frequency, a first multiplier 2 for multiplying the received signal by the output signal of the local oscillator 3, a band-pass filter (BPF) 4 for limiting a band of the output signal of the first multiplier 2, a hopping synthesizer 22 for outputting signals of hopping sequence allocated to a user, a second multiplier 21 for multiplying the output signal of the band-pass filter 4 by the signal of the hopping sequence, a low-pass filter (LPF) 23 for limiting the band of the output signal of the second multiplier 21, a power measuring equipment 24 for measuring a detection power for one bit portion from the output signal of the low-pass filter 23, a hopping sequence phase control circuit 25 for aiming at synchronization of the hopping sequence by controlling the hopping synthesizer 22 on the basis of the result of measurement by the power measuring equipment 24, a differential detection circuit 26 for performing the differential detection of the output signal of the low-pass filter 23 by means of a one-bit delay element 27 and a third multiplier 28, and a code discriminator 9 for discriminating a detected code.
In this receiver, the FFHSS signal received by the receiving antenna 1 is multiplied by a sinusoidal wave signal of a frequency f.sub.RF -f.sub.IF generated by the local oscillator 3 using the first multiplier 2 and the band is limited with the band-pass filter 4, thereby to convert the received signal into a signal in an intermediate frequency band having a central frequency at f.sub.IF.
Next, the signal is multiplied by the output signal generated by the hopping synthesizer 22 using the second multiplier 21 and is applied with band limitation by means of the low-pass filter 23. The hopping synthesizer 22 outputs a signal in which the frequency changes along with the time in accordance with the hopping sequence allocated to respective users. As a result, the received signal that has been applied with frequency hopping is converted into the original narrow-band signal. This operation is referred to as despread.
The timing of the hopping sequence outputted from the hopping synthesizer 22 has to be synchronized with the timing of the hopping sequence of the received signal. This synchronization acquisition is performed as described hereunder.
A signal after despread is inputted to the power measuring equipment 24, squared and integrated for one bit interval, thereby to obtain a detection power for one bit portion. Then, the timing of the hopping sequence outputted from the hopping synthesizer 22 is delayed by one chip by means of the hopping detection phase control circuit 25, and the signal after despread is squared and integrated for one bit interval again, thereby to obtain the detection power for one bit portion. This operation is repeated so as to search the timing of the hopping sequence in which the largest detection power is obtainable.
When FIG. 1 is taken as an example, "1, 4, 2, 3" is outputted as the hopping sequence in the first one bit period Tb, "3, 1, 4, 2" is outputted in the next one bit period, "2, 3, 1, 4" is outputted in the next one bit period, and "4, 2, 3, 1" is outputted in the next one bit period, thus measuring the detection power in respective bit intervals. When the hopping sequence length is "4", any of the timings of these four hopping sequence coincides with the timing of the hopping sequence in the received signal, and the detection power in the bit interval when the hopping sequence of the coincident timing are outputted shows the peak value.
Thereafter, synchronization of the hopping sequence is maintained by outputting the hopping sequence in the coincident timing from the hopping synthesizer 22.
The despread signal is detected in the next place. Here, it is assumed that a PSK system is used for primary modulation, and a differential detection system is used for detection. Detection is made by means of the differential detection circuit 26 composed of the one-bit delay element 27 and the third multiplier 28, and then code decision is made by the code discriminator 9, thereby to discriminate the code. When an FSK system is used as the primary modulation system, a frequency discriminator is used in place of the differential detection circuit 26.
In the conventional fast frequency hopping spread spectrum receiver, however, the detection power sample is given only once per the bit period Tb (sec) to the hopping sequence phase control circuit 25 in synchronization acquisition of the hopping sequence. As a result, the time M.multidot.Tb (sec) becomes necessary for the hopping sequence phase control circuit 25 to obtain M (hopping sequence length) pieces of detection power samples, thus requiring the time of M.multidot.Tb or longer for the synchronization acquisition.
The time required for the synchronization acquisition of the hopping sequence is increased as the number of chips (i.e., M) per one bit is increased. As a result, it becomes necessary to add training data for longer synchronization acquisition before communication is started, and the utilization efficiency of the communication circuit is lowered.